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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Theodoropoulos, D. Kuzmanov, G. Gayd, G. |
| Copyright Year | 2009 |
| Description | Author affiliation: Computer Engineering Laboratory, EEMCS, TU Delft, P.O. Box 5031, 2600 GA, The Netherlands (Theodoropoulos, D.; Kuzmanov, G.; Gayd, G.) |
| Abstract | In this paper, we propose a reconfigurable and scalable hardware accelerator for 3D-audio systems based on the Wave Field Synthesis technology. Previous related work reveals that WFS sound systems are based on using standard PCs. However, two major obstacles are the relative low number of real-time sound sources that can be processed and the high power consumption. The proposed accelerator alleviates these limitations by its performance and energy efficient design. We propose a scalable organization comprising multiple rendering units (RUs), each of them independently processing audio samples. The processing is done in an environment of continuously varying number of sources and speakers. We provide a comprehensive study on the design trade-offs with respect to this multiplicity of sources and speakers. A hardware prototype of our proposal was implemented on a Virtex4FX60 FPGA operating at 200 MHz. A single RU can achieve up to 7× WFS processing speedup compared to a software implementation running on a Pentium D at 3.4 GHz, while consuming, according to Xilinx XPower, approximately 3 W of power only. |
| Starting Page | 1 |
| Ending Page | 8 |
| File Size | 426095 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781424437511 |
| ISSN | 15302075 |
| DOI | 10.1109/IPDPS.2009.5161218 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-05-23 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Audio systems Loudspeakers Energy consumption Hardware Personal communication networks Laboratories Prototypes Field programmable gate arrays Signal synthesis Frequency estimation |
| Content Type | Text |
| Resource Type | Article |
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