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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Nakano, K. Kawakami, K. Shigemoto, K. |
| Copyright Year | 2009 |
| Description | Author affiliation: Department of Information Engineering, Hiroshima University, Kagamiyama 1-4-1, Higashi, JAPAN (Nakano, K.; Kawakami, K.; Shigemoto, K.) |
| Abstract | The main contribution of this paper is to present efficient hardware algorithms for the modulo exponentiation $P^{E}$ mod M used in RSA encryption and decryption, and implement them on the FPGA. The key ideas to accelerate the modulo exponentiation are to use the Montgomery modulo multiplication on the redundant radix-64K number system in the FPGA, and to use embedded 18 × 18-bit multipliers and embedded 18k-bit block RAMs in effective way. Our hardware algorithms for the modulo exponentiation for R-bit numbers P, E, and M can run in less than (2R + 4)(R/16 + 1) clock cycles and in expected (1.5R + 4)(R/16 +1) clock cycles. We have implemented our modulo exponentiation hardware algorithms on Xilinx VirtexII Pro family FPGA XC2VP30-6. The implementation results shows that our hardware algorithm for 1024-bit modulo exponentiation can be implemented to run in less than 2.521ms and in expected 1.892ms. |
| Starting Page | 1 |
| Ending Page | 8 |
| File Size | 184824 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781424437511 |
| ISSN | 15302075 |
| DOI | 10.1109/IPDPS.2009.5160883 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2009-05-23 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Cryptography Field programmable gate arrays Hardware Clocks Adders Acceleration Delay effects Circuits Added delay Arithmetic |
| Content Type | Text |
| Resource Type | Article |
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