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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Schaffer, K. Walker, R.A. |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Comput. Sci., Kent State Univ., Kent, OH (Schaffer, K.; Walker, R.A.) |
| Abstract | The latency of broadcast/reduction operations has a significant impact on the performance of SIMD processors. This is especially true for associative programs, which make extensive use of global search operations. Previously, we developed a prototype associative SIMD processor that uses hardware multithreading to overcome the broadcast/reduction latency. In this paper we show, through simulations of the processor running an associative program, that hardware multithreading is able to improve performance by increasing system utilization, even for processors with hundreds or thousands of processing elements. However, the choice of thread scheduling policy used by the hardware is critical in determining the actual utilization achieved. We consider three thread scheduling policies and show that a thread scheduler that avoids issuing threads that will stall due to pipeline dependencies or thread synchronization operations is able to maintain system utilization independent of the number of threads. |
| Starting Page | 1 |
| Ending Page | 7 |
| File Size | 246732 |
| Page Count | 7 |
| File Format | |
| ISBN | 9781424416936 |
| ISSN | 15302075 |
| DOI | 10.1109/IPDPS.2008.4536349 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-04-14 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware Multithreading Broadcasting Delay Concurrent computing Yarn Computer aided instruction Processor scheduling Synchronization Computer science |
| Content Type | Text |
| Resource Type | Article |
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