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A prototype multithreaded associative SIMD processor, in (2007)
| Content Provider | CiteSeerX |
|---|---|
| Author | Schaffer, Kevin Walker, Robert A. |
| Description | The performance of SIMD processors is often limited by the time it takes to transfer data between the centralized control unit and the parallel processor array. This is especially true of hybrid SIMD models, such as associative computing, that make extensive use of global search operations. Pipelining instruction broadcast can help, but is not enough to solve the problem, especially for massively parallel processors with thousands of processing elements. In this paper, we describe a SIMD processor architecture that combines a fully pipelined broadcast/reduction network with hardware multithreading to reduce performance degradation as the number of processors is scaled up. 1. |
| File Format | |
| Language | English |
| Publisher Date | 2007-01-01 |
| Publisher Institution | Proc. of the 21st IPDPS (Workshop on APDCM |
| Access Restriction | Open |
| Subject Keyword | Simd Processor Associative Simd Processor Performance Degradation Broadcast Reduction Network Processing Element Parallel Processor Instruction Broadcast Control Unit Simd Processor Architecture Global Search Operation Parallel Processor Array Hybrid Simd Model Associative Computing Extensive Use |
| Content Type | Text |
| Resource Type | Article |
