NDLI: A software approach to fault detection on programmable systolic arrays

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Proceedings of the Second IEEE Symposium on Parallel and Distributed Processing 1990 (Cat. No.TH0328-5)

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A software approach to fault detection on programmable systolic arrays

Content Provider	IEEE Xplore Digital Library
Author	Hughey, R. Lopresti, D.P.
Copyright Year	1990
Description	Author affiliation: Dept. of Comput. Sci., Brown Univ., Providence, RI, USA (Hughey, R.)
Abstract	Current approaches to fault detection on processor arrays can be classified as hardware-based or algorithmic. The former are particularly rigid while the latter are restricted in their application. The paper presents two versions of general-purpose software fault detection for programmable systolic arrays. The methods automatically transform cell programs to provide fault detection, allowing the user more flexibility than hardware methods and more generality than algorithmic methods. Additionally, since they are based in software, the fault detection can easily be eliminated when ether methods are more appropriate.
Starting Page	523
Ending Page	526
File Size	358742
Page Count	4
File Format	PDF
ISBN	0818620870
DOI	10.1109/SPDP.1990.143596
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-12-09
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault detection Systolic arrays Hardware Registers Application software Fault tolerance Microwave integrated circuits Software algorithms Robustness Software performance
Content Type	Text
Resource Type	Article

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