NDLI: Impact of ECCs on simultaneously switching output noise for on-chip busses of high reliability systems [error correcting codes]

Content Provider	IEEE Xplore Digital Library
Author	Rossi, D. Muccio, A. Nieuwland, A.K. Katoch, A. Metra, C.
Copyright Year	2004
Description	Author affiliation: DEIS, Bologna Univ., Italy (Rossi, D.; Muccio, A.)
Abstract	In this paper, we analyze the impact of error correcting codes (ECCs) on simultaneously switching outputs (SSO) noise, for the case of a realistic bus of a high reliability system. First, we analyze the effect of different bus transitions on SSO noise. Then we show how different ECCs, requiring a different number of check bits, impact the SSO noise. We prove that Hamming codes cause less noise than the ECCs that have been proposed so far to reduce power consumption and crosstalk-induced delay. In particular, we show that the code requirements for crosstalk and power minimization in terms of switching activity of adjacent wires are opposite to those for SSO noise reduction. Our analysis has been performed considering realistic bus and power supply network models, both implemented using a standard 0.25 /spl mu/m CMOS technology.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	135
Ending Page	140
File Size	793087
Page Count	6
File Format	PDF
ISBN	0769521800
DOI	10.1109/OLT.2004.1319671
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-07-14
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip Error correction codes Crosstalk Noise reduction CMOS technology Power system reliability Energy consumption Delay Wires Performance analysis
Content Type	Text
Resource Type	Article

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