NDLI: A model for transient fault propagation in combinatorial logic

Content Provider	IEEE Xplore Digital Library
Author	Omana, M. Papasso, G. Rossi, D. Metra, C.
Copyright Year	2003
Description	Author affiliation: DEIS, Bologna Univ., Italy (Omana, M.; Papasso, G.; Rossi, D.; Metra, C.)
Abstract	Transient faults (TFs) are increasingly affecting micro-electronic devices as their size decreases. During the design phase, the robustness of circuits for high reliability applications with respect to this kind of faults is generally validated through simulations. However, traditional HSPICE like simulators are too slow for the task of simulating the effects of TFs on large circuits. In this paper, we present a novel mathematical model to accurately estimate the possible propagation of transient fault-due glitches through a CMOS combinational circuit, which is suitable to be used into a new simulation tool able to provide good accuracy, while significantly speeding up simulations, with respect to HPSICE. In particular, our model allows approximately 90% accuracy with respect to HSPICE simulations.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	111
Ending Page	115
File Size	398976
Page Count	5
File Format	PDF
ISBN	0769519687
DOI	10.1109/OLT.2003.1214376
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-07-07
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit simulation Circuit faults Logic devices Microelectronics Mathematical model Combinational circuits Voltage Silicon Aerospace electronics Charge carrier processes
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A stochastic model for fault propagation, in combinational circuits

A fast fault simulation algorithm for combinational circuits

SEAT-LA: a soft error analysis tool for combinational logic

A reconvergent fanout analysis for efficient exact fault simulation of combinational circuits

Combinational circuit fault diagnosis using logic emulation

High speed lateral-IGBT with a passive gate

Fanout fault analysis for digital logic circuits

A model for transient fault propagation considering glitch amplitude and rise-fall time mismatch

Diagnosis of single gate delay faults in combinational circuits using delay fault simulation

A model for transient fault propagation in combinatorial logic

Similar Documents

A stochastic model for fault propagation, in combinational circuits

A fast fault simulation algorithm for combinational circuits

SEAT-LA: a soft error analysis tool for combinational logic

A reconvergent fanout analysis for efficient exact fault simulation of combinational circuits

Combinational circuit fault diagnosis using logic emulation

High speed lateral-IGBT with a passive gate

Fanout fault analysis for digital logic circuits

A model for transient fault propagation considering glitch amplitude and rise-fall time mismatch

Diagnosis of single gate delay faults in combinational circuits using delay fault simulation

A model for transient fault propagation in combinatorial logic