NDLI: 325GHz CPW band pass filter integrated in advanced HR SOI RF CMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Gianesello, F. Pilard, R. Lepilliet, S. Waldhoff, N. Durand, C. Boret, S. Martineau, B. Dambrine, G. Gloria, D. Rauber, B. Raynaud, C.
Copyright Year	2010
Description	Author affiliation: STMicroelectronics, TR&D, TPS Lab, 850 avenue Jean Monnet, 38926 Crolles, France (Gianesello, F.; Pilard, R.; Durand, C.; Boret, S.; Martineau, B.; Gloria, D.; Rauber, B.; Raynaud, C.) \|\| IEMN, cité scientifique, avenue Poincaré, BP69, 59662 Villeneuve d'Ascq, France (Lepilliet, S.; Waldhoff, N.; Dambrine, G.)
Abstract	Today, measurement of 65nm CMOS [1] and 130nm-based SiGe HBTs [2] technologies demonstrate both fT (current gain cut-off frequency) and fmax (maximum oscillation frequency) higher than 200 GHz, which are clearly comparable to advanced commercially available 100nm III–V HEMT. This increase allows new millimeter wave (MMW) applications on silicon. One of the success keys is then the passive integration. In this paper, on-chip coplanar waveguides (CPWs), which have been achieved in STMicroelectronics advanced nanometric RF CMOS High Resistivity (HR) SOI (ρ> 1kΩ·cm) process, and characterized up to 325GHz are reported. Moreover, for the first time passive circuits working @ 325GHz have been achieved on silicon and characterized demonstrating state-of-the-art performances and good agreement with electric simulations.
Starting Page	57
Ending Page	60
File Size	359033
Page Count	4
File Format	PDF
ISBN	9781424472321
e-ISBN	9782874870163
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-09-28
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	EUROPEAN MICROWAVE ASSOC
Subject Keyword	Coplanar waveguides Silicon CMOS integrated circuits Band pass filters CMOS technology Substrates Bandwidth
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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