NDLI: High-precision TDC in an FPGA using a 192 MHz quadrature clock

Content Provider	IEEE Xplore Digital Library
Author	Fries, M.D. Williams, J.J.
Copyright Year	2003
Description	Author affiliation: Functional Imaging Modality, Gen. Electr. Med. Syst., Waukesha, WI, USA (Fries, M.D.; Williams, J.J.)
Abstract	The basic principle involved in a Positron Emission Tomography (PET) medical imaging scanner is the annihilation of a positron-electron pair within a body that produces a pair of gamma-ray photons. An FPGA is used to process gamma-ray event inputs from a PET detector. An analog circuit compares the incoming gamma-ray event pulse to a threshold and produces a trigger pulse when above the threshold. A digital TDC circuit, timed with a 192 MHz quadrature clock, resides inside the event processing FPGA and measures the arrival time of this pulse. The TDC circuit does this by running a quadrature counter that is latched synchronously by a trigger pulse edge detection circuit, also running in quadrature. Meta-stability is limited to one quarter clock cycle of the trigger pulse edge circuit. The TDC circuit has a requirement to measure the arrival time with a spread based on repeated conversions of /spl plusmn/2 LSB of the 192 MHz quadrature clock (1.302 nS), a standard deviation based on repeated conversions of less than 1/2 LSB, and a differential non-linearity of less than /spl plusmn/1/2 LSB.
Starting Page	580
Ending Page	584
File Size	408921
Page Count	5
File Format	PDF
ISBN	0780376366
DOI	10.1109/NSSMIC.2002.1239380
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-11-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Clocks Pulse circuits Positron emission tomography Pulse measurements Time measurement Biomedical imaging Single photon emission computed tomography Event detection Gamma ray detection
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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