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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Lopes, N. Ribeiro, B. Goncalves, J. |
| Copyright Year | 2012 |
| Description | Author affiliation: CISUC - Center for Informatics and Systems of University of Coimbra, Portugal (Lopes, N.; Ribeiro, B.; Goncalves, J.) |
| Abstract | Deep learning architecture models by contrast with shallow models draw on the insights of biological inspiration which has been a challenge since the inception of the idea of simulating the brain. In particular their (many) hierarchical levels of composition track the development of parallel implementation in an attempt to become accessibly fast. When it comes to performance enhancement Graphics Processing Units (GPU) have carved their own strength in machine learning. In this paper, we present an approach that relies mainly on three kernels for implementing both the Restricted Boltzmann Machines (RBM) and Deep Belief Networks (DBN) algorithms. Instead of considering the neuron as the smallest unit of computation each thread represents the connection between two (one visible and one hidden) neurons. Although conceptually it may seem weird, the rationale behind is to think of a connection as performing a simple function that multiplies the clamped input by its weight. Thus, we maximize the GPU workload avoiding idle cores. Moreover, we placed great emphasis on the kernels to avoid uncoalesced memory accesses as well as to take advantage of the shared memory to reduce global memory accesses. Additionally, our approach uses a step adaptive learning rate procedure which accelerates convergence. The approach yields very good speedups (up to 46×) as compared with a straightforward implementation when both GPU and CPU implementations are tested on the MINST database. |
| Starting Page | 1 |
| Ending Page | 7 |
| File Size | 1062314 |
| Page Count | 7 |
| File Format | |
| ISBN | 9781467314886 |
| ISSN | 21614393 |
| e-ISBN | 9781467314909 |
| e-ISBN | 9781467314893 |
| DOI | 10.1109/IJCNN.2012.6252431 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2012-06-10 |
| Publisher Place | Australia |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Kernel Graphics processing unit Instruction sets Computer architecture Training Neurons Vectors |
| Content Type | Text |
| Resource Type | Article |
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