NDLI: Robust phase locked loops optimized for DSP implementation in power quality applications

Content Provider	IEEE Xplore Digital Library
Author	Freijedo, F.D. Doval-Gandoy, J. Lopez, O. Cabaleiro, J.
Copyright Year	2008
Description	Author affiliation: Dept. of Electron. Technol., Univ. of Vigo, Vigo (Freijedo, F.D.; Doval-Gandoy, J.; Lopez, O.; Cabaleiro, J.)
Abstract	Phase locked loop (PLL) algorithms for grid synchronization are a very important part of the control in most of the grid-connected power converters applications. The performance of the PLL should not be much affected under distorted grid conditions: the presence of harmonics, unbalance, noise, etc in the inputs should not distort PLL measurements. This paper presents an optimized design approach of PLLs, both for single-phase and three-phase systems. The loop filter of the PLL sets its dynamic response; the loop filter should be tuned in order to achieve a correct tradeoff between transient response and harmonics/noise cancellation. This paper proposes the use of notch filters inside the loop in order to optimize the PLL performance; this approach is suitable both for single-phase and three-phase PLLs. Another novel interesting proposal of this paper is the implementation of the digitally controlled oscillator (DCO): the digital model of a sinusoidal oscillator is implemented, instead trigonometric functions. This reduces the needed digital resources without reducing the performance. This approach is specially useful for DSP-based control of power converters. The proposed PLLs have been implemented and tested in a fixed point DSP (TI TMS320LF2407) and also in a floating point microprocessor (PowerPC of the dSpace DS1103). The systems have been tested with different distorted inputs in order to check the validity of the design approaches and good results have been obtained.
Starting Page	3052
Ending Page	3057
File Size	600005
Page Count	6
File Format	PDF
ISBN	9781424417674
ISSN	1553572X
DOI	10.1109/IECON.2008.4758447
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Robustness Phase locked loops Digital signal processing Power quality Power harmonic filters Harmonic distortion Oscillators Distortion measurement Noise measurement Design optimization
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

DSP Implementation of Three-Phase PLL using Modified Synchronous Reference Frame

DSP/FPGA implementation of a phase locked loop for digital power electronics

Design, analysis and implementation of DSP based single-phase shunt active filter controller

Implementation of High-Dynamic Phase-Locked Loop Based on DSP

An Optimized Implementation of Phase Locked Loops for Grid Applications

Frequency Determination in a Single-Phase Voltage Signal using Adaptative Notch Filters

A 150-MHz translinear phase-locked loop

A new PLL synthesizer for fast FH spread spectrum communications

Fast DC component suppression method for phase locked loop

Robust phase locked loops optimized for DSP implementation in power quality applications

Similar Documents

DSP Implementation of Three-Phase PLL using Modified Synchronous Reference Frame

DSP/FPGA implementation of a phase locked loop for digital power electronics

Design, analysis and implementation of DSP based single-phase shunt active filter controller

Implementation of High-Dynamic Phase-Locked Loop Based on DSP

An Optimized Implementation of Phase Locked Loops for Grid Applications

Frequency Determination in a Single-Phase Voltage Signal using Adaptative Notch Filters

A 150-MHz translinear phase-locked loop

A new PLL synthesizer for fast FH spread spectrum communications

Fast DC component suppression method for phase locked loop

Robust phase locked loops optimized for DSP implementation in power quality applications