NDLI: Exploiting parallelism in media processing using VLIW processor

Content Provider	IEEE Xplore Digital Library
Author	Lv, T. Ozer, B. Wolf, W.
Copyright Year	2003
Description	Author affiliation: Dept. of Electr. Eng., Princeton Univ., NJ, USA (Lv, T.; Ozer, B.; Wolf, W.)
Abstract	This paper presents the results of analyzing multimedia applications that have been implemented on a trimedia VLIW processor, TM1300. The TM1300 processor offers several media-specific features, such as multimedia instructions, that experience has shown to be very important for obtaining maximum performance from the VLlW machine. Other researchers have studied the effects of instructions on superscalar machines, but we know of no other work that measures the utilization of real VLIW instruction sets on significant applications. We will study static and dynamic instruction counts, interactions between instructions, and other effects. Our experiments show that a TM1300 processor provides a 5/spl times/ speedup over a single-issue RISC processor in equivalent technology on average and more than 10/spl times/ speedup in best case.
Sponsorship	IEEE Signal Process. Soc
File Size	439885
File Format	PDF
ISBN	0780377508
ISSN	15224880
DOI	10.1109/ICIP.2003.1247190
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-09-14
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	VLIW Process design Instruction sets Hardware Analytical models Reduced instruction set computing Costs Registers Logic
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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