NDLI: Tiered-latency DRAM: A low latency and low cost DRAM architecture

Content Provider	IEEE Xplore Digital Library
Author	Donghyuk Lee Yoongu Kim Seshadri, V. Liu, J. Subramanian, L. Mutlu, O.
Copyright Year	2013
Description	Author affiliation: Carnegie Mellon Univ., Pittsburgh, PA, USA (Donghyuk Lee; Yoongu Kim; Seshadri, V.; Liu, J.; Subramanian, L.; Mutlu, O.)
Abstract	The capacity and cost-per-bit of DRAM have historically scaled to satisfy the needs of increasingly large and complex computer systems. However, DRAM latency has remained almost constant, making memory latency the performance bottleneck in today's systems. We observe that the high access latency is not intrinsic to DRAM, but a trade-off made to decrease cost-per-bit. To mitigate the high area overhead of DRAM sensing structures, commodity DRAMs connect many DRAM cells to each sense-amplifier through a wire called a bitline. These bitlines have a high parasitic capacitance due to their long length, and this bitline capacitance is the dominant source of DRAM latency. Specialized low-latency DRAMs use shorter bitlines with fewer cells, but have a higher cost-per-bit due to greater sense-amplifier area overhead. In this work, we introduce Tiered-Latency DRAM (TL-DRAM), which achieves both low latency and low cost-per-bit. In TL-DRAM, each long bitline is split into two shorter segments by an isolation transistor, allowing one segment to be accessed with the latency of a short-bitline DRAM without incurring high cost-per-bit. We propose mechanisms that use the low-latency segment as a hardware-managed or software-managed cache. Evaluations show that our proposed mechanisms improve both performance and energy-efficiency for both single-core and multi-programmed workloads.
Starting Page	615
Ending Page	626
File Size	3526139
Page Count	12
File Format	PDF
ISBN	9781467355858
ISSN	15300897
e-ISBN	9781467355872
DOI	10.1109/HPCA.2013.6522354
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-02-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transistors Timing DRAM chips Capacitors Capacitance Computer architecture
Content Type	Text
Resource Type	Article

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