NDLI: Power-performance co-optimization of throughput core architecture using resistive memory

Content Provider	IEEE Xplore Digital Library
Author	Goswami, N. Bingyi Cao Tao Li
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL, USA (Goswami, N.; Bingyi Cao; Tao Li)
Abstract	Massively parallel computing on throughput computers such as GPUs requires myriad memory accesses to register files, on-chip scratchpad, caches, and off-chip DRAM. Unlike CPUs, these processors have a large register file and on-chip scratchpad memory, which consume a significant portion of compute core power (35%-45%). In this paper, we introduce novel throughput architecture by integrating resistive memory (Spin Transfer Torque RAM) inside the compute core, which reduces leakage significantly, but introduces write power overhead and longer write latencies in GPU shared memory and register file accesses. We enhance the compute core by introducing register file organization with differential memory update mechanism to remove update redundancy during write operations. Furthermore, using merged register-write-mechanism and write-back buffer, we coalesce multithreaded GPU register write accesses to save write energy. In addition, we introduce hybrid shared memory design using SRAM and STT-MRAM that provides significant leakage/dynamic power savings without affecting performance. On average, across 23 GPGPU/graphics workloads, our schemes save 46% dynamic power due to register access (83% leakage power saving) with negligible performance degradation. On average, hybrid shared memory provides 10% reduction in dynamic power with maximum 1.6× performance improvement for the current workloads at no additional area overhead.
Starting Page	342
Ending Page	353
File Size	4719829
Page Count	12
File Format	PDF
ISBN	9781467355858
ISSN	15300897
e-ISBN	9781467355872
DOI	10.1109/HPCA.2013.6522331
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-02-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Registers Graphics processing units Random access memory Magnetic tunneling Arrays System-on-chip
Content Type	Text
Resource Type	Article

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