NDLI: Efficient instruction schedulers for SMT processors

Content Provider	IEEE Xplore Digital Library
Author	Sharkey, J.J. Ponomarev, D.V.
Copyright Year	2006
Description	Author affiliation: Dept. of Comput. Sci., State Univ. of New York, Binghamton, NY, USA (Sharkey, J.J.; Ponomarev, D.V.)
Abstract	We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently proposed instruction packing to SMT. Instruction packing opportunistically packs two instructions (possibly from different threads), each with at most one non-ready source operand at the time of dispatch, into the same issue queue entry. Our second design, termed 2OP/spl I.bar/BLOCK, takes these ideas one step further and completely avoids the dispatching of the instructions with two non-ready source operands. This technique has several advantages. First, it reduces the scheduling complexity (and the associated delays) as the logic needed to support the instructions with 2 non-ready source operands is eliminated. More surprisingly, 2OP/spl I.bar/BLOCK simultaneously improves the performance as the same issue queue entry may be reallocated multiple times to the instructions with at most one non-ready source (which usually spend fewer cycles in the queue) as opposed to hogging the entry with an instruction which enters the queue with two non-ready sources. For the schedulers with the capacity to hold 64 instructions, the 2OP/spl I.bar/BLOCK design outperforms the traditional queue by 11%, on the average, and at the same time results in a 10% reduction in the overall scheduling delay.
Starting Page	288
Ending Page	298
File Size	430702
Page Count	11
File Format	PDF
ISBN	0780393686
ISSN	15300897
DOI	10.1109/HPCA.2006.1598137
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-02-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Processor scheduling Surface-mount technology Yarn Delay Dynamic scheduling Scalability Throughput Timing Computer science Process design
Content Type	Text
Resource Type	Article

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