NDLI: Software-hardware cooperative memory disambiguation

Content Provider	IEEE Xplore Digital Library
Author	Huang, R. Garg, A. Huang, M.
Copyright Year	2006
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA (Huang, R.; Garg, A.; Huang, M.)
Abstract	In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buffering these instructions requires a tremendous amount of microarchitectural resources. Unfortunately, large structures negatively impact processor clock speed and energy efficiency. Thus, innovations in effective and efficient utilization of these resources are needed. In this paper, we target the load-store queue, a dynamic memory disambiguation logic that is among the least scalable structures in a modern microprocessor. We propose to use software assistance to identify load instructions that are guaranteed not to overlap with earlier pending stores and prevent them from competing for the resources in the load-store queue. We show that the design is practical, requiring off-line analyses and minimum architectural support. It is also very effective, allowing more than 40% of loads to bypass the load-store queue for floating-point applications. This reduces resource pressure and can lead to significant performance improvements.
Starting Page	244
Ending Page	253
File Size	484290
Page Count	10
File Format	PDF
ISBN	0780393686
ISSN	15300897
DOI	10.1109/HPCA.2006.1598133
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-02-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Microarchitecture Clocks Resource management Application software Computer aided instruction Delay Energy consumption Out of order High performance computing
Content Type	Text
Resource Type	Article

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