NDLI: Redundant functional faults reduction by saboteurs synthesis [logic verification]

Content Provider	IEEE Xplore Digital Library
Author	Fummi, F. Marconcini, C. Pravadelli, G.
Copyright Year	2003
Description	Author affiliation: Dipt. di Inf., Verona Univ., Italy (Fummi, F.; Marconcini, C.; Pravadelli, G.)
Abstract	High-level descriptions of digital systems are perturbed by using high-level fault models in order to perform functional verification. Fault lists should be accurately created in order to avoid waste of time during ATPG and fault simulation. However, automatic fault injection tools can insert redundant faults which are not symptoms of design errors. Such redundant faults should be removed from the fault list before starting the verification session. This paper proposes an automatic strategy for high-level faults injection, which removes redundant bit coverage faults. An efficient implementation of a bit coverage saboteur is proposed, which allows one to use synthesis for redundant faults removal. Experimental results highlight the effectiveness of the methodology. By using the proposed injection strategy, functional APTG time is reduced and fault coverage is increased.
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council IEEE Comput. Soc. Design Automation Tech. Committee
Starting Page	108
Ending Page	113
File Size	392165
Page Count	6
File Format	PDF
ISBN	0780382366
DOI	10.1109/HLDVT.2003.1252483
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-11-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware design languages Automatic test pattern generation Redundancy Fault detection Digital systems Software testing Taxonomy Timing Humans Writing
Content Type	Text
Resource Type	Article

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