NDLI: System level testability analysis using Petri nets

Content Provider	IEEE Xplore Digital Library
Author	Tianjing Jiang Klenke, R.H. Aylor, J.H. Gang Han
Copyright Year	2000
Description	Author affiliation: Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA (Tianjing Jiang)
Abstract	The test problem increasingly affects system design costs. One approach for reducing testing difficulties is to consider system testability as early as possible in the design cycle. The technique described herein adds a testability analysis capability to the ADEPT high-level performance modeling environment. This capability provides the designer with feedback on the testability of the specific architecture being modeled at an abstract level. The testability information is expressed in the form of measures of the relative controllability and observability of signals in the system architecture. The testability information is derived from reachability graph analysis of the corresponding Petri net representation of the system architecture. This methodology has the potential to provide valuable assistance in designing systems which have lower cost, higher performance, and which also meet testability requirements.
Starting Page	112
Ending Page	117
File Size	567549
Page Count	6
File Format	PDF
ISBN	0769507867
DOI	10.1109/HLDVT.2000.889570
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-11-10
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System testing Petri nets Costs Controllability Observability Performance analysis Feedback Systems engineering and theory Process design Space exploration
Content Type	Text
Resource Type	Article

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