NDLI: An efficient scheduling mechanism with flow-based packet reordering in a high-speed network processor

Content Provider	IEEE Xplore Digital Library
Author	Beibei Wu Yang Xu Bin Liu Hongbin Lu Xiaojun Wang
Copyright Year	2005
Description	Author affiliation: Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China (Beibei Wu; Yang Xu; Bin Liu; Hongbin Lu)
Abstract	In most network processors (NP), multiple CPU cores are employed to exploit packet level parallelism, where high processing resource utilization and within-flow packet order preservation are two fundamental design targets. However, while many researches are only focused on the first one, the second has not been solved perfectly. In this paper, a high-speed NP architecture is proposed to handle both of the two issues simultaneously, where a centralized state controller with hardware flow chains is employed to schedule the CPU cores fairly and to transmit the packets orderly. We also introduce local memory to increase CPU utilization as well as to store packets that can't be sent out immediately due to flow constraints. We implement the NP prototype with an FPGA, upon which a series of experiments are carried out, and the results indicate that it can achieve both of the two goals perfectly.
Starting Page	481
Ending Page	485
File Size	1023636
Page Count	5
File Format	PDF
ISBN	0780389247
DOI	10.1109/HPSR.2005.1503279
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-05-12
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Processor scheduling Intelligent networks High-speed networks Hardware Engines Computer science Cities and towns Parallel processing Resource management Centralized control
Content Type	Text
Resource Type	Article

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