NDLI: S3-P4: Impact of drain conductance in InGaaS-HEMTs operated in a class-F amplifier

Content Provider	IEEE Xplore Digital Library
Author	Yoshida, T. Otsuji, T. Suemitsu, T. Oyama, M. Watanabe, K. Umeda, Y.
Copyright Year	2014
Description	Author affiliation: Res. Inst. of Electr. Commun., Tohoku Univ., Sendai, Japan (Yoshida, T.; Otsuji, T.; Suemitsu, T.) \|\| Dept. of Electr. Eng., Tokyo Univ. of Sci., Noda, Japan (Oyama, M.; Watanabe, K.; Umeda, Y.)
Abstract	The Power Added Efficiency (PAE) of amplifiers operated in wave bands, such as 60 GHz, is still under 30%. A switching type amplifier consisting of ultrahigh-frequency transistors is a promising way to improve PAE. Therefore we proposed 60-GHz-band class-F amplifier with InGaAs-based high electron mobility transistors (HEMTs). In such high frequencies, the parasitic delay time is the main cause of degradation of the RF characteristics in HEMTs. In this paper, we characterized the parasitic gate delay time when the device is operated on the load line of the class-F amplifier. This result suggests us that the drain conductance affects the degradation of parasitic delay time at low drain bias condition on the load line. Hence the reduction of the source resistance and drain resistance is also important as well as the reduction of capacitance in order to improve the total performance of the amplifier.
Starting Page	1
Ending Page	4
File Size	1639579
Page Count	4
File Format	PDF
ISBN	9781479964413
DOI	10.1109/LEC.2014.6951560
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-08-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delays Logic gates HEMTs MODFETs Harmonic analysis Resistance Millimater Wave InGaAs-HEMTs Delay time anarysis Class F PAE
Content Type	Text
Resource Type	Article

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