NDLI: Distance-aware round-robin mapping for large NUCA caches

Content Provider	IEEE Xplore Digital Library
Author	Ros, A. Cintra, M. Acacio, M.E. Garcia, J.M.
Copyright Year	2009
Description	Author affiliation: School of Informatics, University of Edinburgh (Cintra, M.) \|\| Departamento de Ingeniería y Tecnología de Computadores, Universidad de Murcia, 30100 Murcia (Spain) (Ros, A.; Acacio, M.E.; Garcia, J.M.)
Abstract	In many-core architectures, memory blocks are commonly assigned to the banks of a NUCA cache by following a physical mapping. This mapping assigns blocks to cache banks in a round-robin fashion, thus neglecting the distance between the cores that most frequently access every block and the corresponding NUCA bank for the block. This issue impacts both cache access latency and the amount of on-chip network traffic generated. On the other hand, first-touch mapping policies, which take into account distance, can lead to an unbalanced utilization of cache banks, and consequently, to an increased number of expensive off-chip accesses. In this work, we propose the distance-aware round-robin mapping policy, an OS-managed policy which addresses the trade-off between cache access latency and number of off-chip accesses. Our policy tries to map the pages accessed by a core to its closest (local) bank, like in a first-touch policy. However, our policy also introduces an upper bound on the deviation of the distribution of memory pages among cache banks, which lessens the number of off-chip accesses. This tradeoff is addressed without requiring any extra hardware structure. We also show that the private cache indexing commonly used in many-core architectures is not the most appropriate for OS-managed distance-aware mapping policies, and propose to employ different bits for such indexing. Using GEMS simulator we show that our proposal obtains average improvements of 11% for parallel applications and 14% for multi-programmed workloads in terms of execution time, and significant reductions in network traffic, over a traditional physical mapping. Moreover, when compared to a first-touch mapping policy, our proposal improves average execution time by 5% for parallel applications and 6% for multi-programmed workloads, slightly increasing on-chip network traffic.
Starting Page	79
Ending Page	88
File Size	208115
Page Count	10
File Format	PDF
ISBN	9781424449224
e-ISBN	9781424449217
DOI	10.1109/HIPC.2009.5433220
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-16
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Tiles Delay Telecommunication traffic Proposals Indexing Organizing Physics computing Informatics Computer architecture Memory architecture
Content Type	Text
Resource Type	Article

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