NDLI: Energy frugal tags in reprogrammable I-caches for application-specific embedded processors

Content Provider	IEEE Xplore Digital Library
Author	Petrov, P. Orailoglu, A.
Copyright Year	2002
Description	Author affiliation: CSE Dept., Univ. of California at San Diego, CA, USA (Petrov, P.; Orailoglu, A.)
Abstract	Presents a software-directed customization methodology for minimizing the energy dissipation in the instruction cache (I-cache), one of the most power-consuming microarchitectural components of high-end embedded processors. We target particularly the instruction cache tag operations and show how an exceedingly small number of tag bits, if any, are needed to compute the miss/hit behavior for the most frequently executed application loops, thus minimizing the energy needed to perform the tag reads and comparisons. The proposed methodology exploits the fact that the code layout structure of the program loops can be identified after compile and link, and that it typically resides in a very confined memory location, for which very few bits from the effective address can be utilized as a tag. Subsequently, we present an efficient, programmable implementation to apply the suggested energy minimization technique. The experimental results show a significant decrease in energy dissipation for a set of real-life applications.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Design Autom. IEEE Comput. Soc. Tech. Council on Software Eng. IEEE Circuits & Syst. Soc. IFIP WG 10.5 ACM SIG Software Eng. ACM SIG Design Autom
Starting Page	181
Ending Page	186
File Size	501486
Page Count	6
File Format	PDF
ISBN	1581135424
DOI	10.1109/CODES.2002.1003622
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-05-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Technical Activities Guide -TAG Energy consumption Microarchitecture System-on-a-chip Time to market Personal digital assistants Permission Hardware Costs Silicon
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Energy frugal tags in reprogrammable I-caches for application-specific embedded processors

Energy frugal tags in reprogrammable i-caches for application-specific embedded processors (2002).

ABSTRACT Energy Frugal Tags in Reprogrammable I-Caches for Application-Specific Embedded Processors-

Data cache energy minimizations through programmable tag size matching to the applications

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A low power hardware/software partitioning approach for core-based embedded systems

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Energy frugal tags in reprogrammable I-caches for application-specific embedded processors

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