NDLI: Power aware SID-based simulator for embedded multicore DSP subsystems

Content Provider	IEEE Xplore Digital Library
Author	Cheng-Yen Lin Po-Yu Chen Chun-Kai Tseng Chung-Wen Huang Chia-Chieh Weng Chi-Bang Kuan Shih-Han Lin Shi-Yu Huang Jenq-Kuen Lee
Copyright Year	2010
Description	Author affiliation: National Tsing-Hua University, Hsin-Chu, Taiwan (Cheng-Yen Lin; Po-Yu Chen; Chun-Kai Tseng; Chung-Wen Huang; Chia-Chieh Weng; Chi-Bang Kuan; Shih-Han Lin; Shi-Yu Huang; Jenq-Kuen Lee)
Abstract	The embedded multicore DSP systems are playing increasingly important role for consumer electronic design. Such systems try to optimize the objective for both performance and power with mobile devices. Embedded application developers will then devise designs to optimize embedded applications for not only performance but also power. However, currently there are no power metrics support for popular application design platforms such as QEMU and SID, where application developers develop their applications. This hinders application developers to help tune optimizations for power. In this paper, we propose a power aware simulation framework on embedded multicore DSP subsystems for SID framework. To the best of our knowledge, this is the first work to attempt to build a power aware simulator based on SID simulation framework. The power estimation flow includes two phases, IP level power modeling and system level power prower profiling. In the IP level power modeling, $PowerMixer^{IP}$ is employed to build up the power model for PAC DSP and major IPs. In the system level power profiling, we provide a power profiling hierarchy that meets the demand of embedded software developers. The granularity of power profiling can be configured to the whole simulation stage or any specific time slot in the simulation such as a dedicated function loop. In our experiments, DSP programs with SIMD intrinsics for DSPStone benchmark are examined with our proposed power aware simulator. In addition, a face detection application is deployed as a running example on multi-core DSP systems to show how our power simulator can be used to help collaborate with developers in the optimization process to illustrate views of power dissipations of applications.
Starting Page	95
Ending Page	103
File Size	1410718
Page Count	9
File Format	PDF
ISBN	9781605589053
e-ISBN	9781605589053
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-10-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Multicore processing Random access memory Artificial neural networks Digital signal processing Switches DSP Multicore Simulation Power Embedded Processor
Content Type	Text
Resource Type	Article

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