NDLI: NXG06-3: The Central-stage Buffered Clos-Network to Emulate an OQ Switch

Content Provider	IEEE Xplore Digital Library
Author	Feng Wang Wenqi Zhu Hamdi, M.
Copyright Year	2006
Description	Author affiliation: Dept. of Comput. Sci., Hong Kong Univ. of Sci. & Technol., Kowloon (Feng Wang; Wenqi Zhu; Hamdi, M.)
Abstract	In this paper, we propose a highly scalable packet switch that is based on a multi-stage multi-layer architecture made up of many modest size switches. This new architecture resembles the famous Clos-network studied in circuit switching systems except that it has distributed shared memories in the central stage. We call it central-stage buffered Clos-network (CBC). We first analyze the memory requirements for the CBC to emulate an output-queued (OQ) switch since OQ switches are generally regarded as having the optimal delay-throughput performance. Then we design an efficient packet-scheduling algorithm for the CBC to emulate an FCFS OQ switch. We show two distinguished features of this algorithm. First, it converges to the maximum matching faster than any other scheduling algorithms using the same paradigm. Secondly, the performance of the algorithm is independent of any arriving traffic pattern, which is not seen in other scheduling algorithms, such as iSLIP, DRRM and so on...
Starting Page	1
Ending Page	5
File Size	282376
Page Count	5
File Format	PDF
ISBN	1424403561
ISSN	1930529X
DOI	10.1109/GLOCOM.2006.349
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-11-27
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Scheduling algorithm Packet switching Algorithm design and analysis Switching systems Delay Communication switching Computer architecture Circuits Performance analysis
Content Type	Text
Resource Type	Article

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