NDLI: An optimized digital modem architecture for VLSI implementation

Content Provider	IEEE Xplore Digital Library
Author	Hu, V.
Copyright Year	1990
Description	Author affiliation: LinCom Corp., Los Angeles, CA, USA (Hu, V.)
Abstract	Investigation into recently published research has uncovered a number of digital signal processing algorithms which have excellent performance characteristics and are well suited for VLSI implementation. The result of this investigative effort is an optimized modem signal processing architecture that is applicable to a variety of digital phase modulation schemes and that utilizes a combination of these techniques for signal generation, detection, and synchronization. The baseband signal processing functions which will be implemented in a VLSI gate array are described. The baseband digital signal processing architecture adopted in both the modulation and demodulation functions provides multirate capability by employing the principle of sample rate conversion. The demodulator signal processing features coherent adaptive matched filter detection and maximum likelihood symbol and carrier synchronization algorithms.
Starting Page	1691
Ending Page	1695
File Size	419016
Page Count	5
File Format	PDF
ISBN	0879426322
DOI	10.1109/GLOCOM.1990.116461
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1990-12-02
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Modems Very large scale integration Signal processing algorithms Digital signal processing Array signal processing Baseband Adaptive signal processing Demodulation Maximum likelihood detection Phase modulation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Digital signal processing in a LSI 4.8 kbit/s modem

A Flexible VLSI Architecture for Extracting Diversity and Spatial Multiplexing Gains in MIMO Channels

Architecture for DSP VLSI

VLSI digital demodulator co-processor

Dual Mode K-Best MIMO Detector Architecture and VLSI Implementation

Optimized VLIW architecture for non-zero IF QAM-modem implementations

An All Digital Demodulator using Off-the-Shelf VLSI Technology

A VLSI array CORDIC architecture

VLSI implementation of an area-efficient architecture for the Viterbi algorithm

An optimized digital modem architecture for VLSI implementation

Similar Documents

Digital signal processing in a LSI 4.8 kbit/s modem

A Flexible VLSI Architecture for Extracting Diversity and Spatial Multiplexing Gains in MIMO Channels

Architecture for DSP VLSI

VLSI digital demodulator co-processor

Dual Mode K-Best MIMO Detector Architecture and VLSI Implementation

Optimized VLIW architecture for non-zero IF QAM-modem implementations

An All Digital Demodulator using Off-the-Shelf VLSI Technology

A VLSI array CORDIC architecture

VLSI implementation of an area-efficient architecture for the Viterbi algorithm

An optimized digital modem architecture for VLSI implementation