NDLI: Data-aided ML parameter estimators for PSK burst modems and their systolic VLSI implementations

Content Provider	IEEE Xplore Digital Library
Author	Jiang, Y. Verahrami, F.B. Wen-Chun Ting Richmond, R.L. Baras, J.S.
Copyright Year	1999
Description	Author affiliation: Hughes Network Syst. Inc., Germantown, MD, USA (Jiang, Y.)
Abstract	A high performance Universal Modem ASIC that supports several modulation types and burst mode frame formats is under development. Powerful and generic data-aided (DA) parameter estimators are necessary to accommodate many modes. In this paper we present an approximated maximum likelihood (ML) carrier frequency offset estimator, ML joint carrier phase and timing offsets estimator and their systolic VLSI implementations for PSK burst modems. The performances are close to the Cramer-Rao lower bounds (CRLB) at low SNRs. Compared with theoretical solutions the estimators proposed here are much simpler and easier to implement by the current VLSI technology. The CRLB for DA estimations is discussed in some depth, some issues on training sequence design is also addressed in this work.
Starting Page	2177
Ending Page	2182
File Size	418834
Page Count	6
File Format	PDF
ISBN	0780357965
DOI	10.1109/GLOCOM.1999.827590
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-12-05
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Maximum likelihood estimation Parameter estimation Phase shift keying Modems Frequency estimation Phase estimation Very large scale integration Application specific integrated circuits Timing Estimation theory
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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