NDLI: Implementation architecture of a variable forward error correction decoder

Content Provider	IEEE Xplore Digital Library
Author	Yuming Lu Brodersen, R.
Copyright Year	1998
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA (Yuming Lu)
Abstract	As the demand for wireless transmission of multimedia data increases, simple application of a single FEC code is not adequate to meet the unique requirements of multiple data types, as these data types often have highly variable error tolerances. Variable forward error correction (VFEC) is a technique of applying a family of FEC codes with a wide range of coding rates to provide unequal error protection. In this implementation, we achieve VFEC by adopting the family of 63-bit binary BCH codes which are generated by the finite field GF(2/sup 6/). Since the primary implementation challenge of an error correction system is often concentrated on the decoder design, this paper is devoted to defining a VFEC decoder architecture. By exploiting the redundancies between these codes, we observe that a majority of the decoder hardware can be reused among codes, resulting in an implementation that is only slightly more complicated than a single FEC decoder. In this paper, an architecture and the control logic for a single binary BCH decoder is presented, which can then be extended to a VFEC decoder design.
Starting Page	2840
Ending Page	2847
File Size	398438
Page Count	8
File Format	PDF
ISBN	0780349849
DOI	10.1109/GLOCOM.1998.776587
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-11-08
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Forward error correction Decoding Error correction codes Error correction Hardware Galois fields Redundancy Logic design Bit error rate Control systems
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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