NDLI: A high-speed ATM switch architecture using random access input buffers and multi-cell-time arbitration

Content Provider	IEEE Xplore Digital Library
Author	Hakyong Kim Changhwan Oh Kiseon Kim
Copyright Year	1997
Description	Author affiliation: Dept. of Inf. & Commun., Kwang-Ju Inst. of Sci. & Technol., South Korea (Hakyong Kim)
Abstract	We introduce a new high-speed ATM switch using random access input buffers (RAIB) and multi-cell-time arbitration (MCTA), and evaluate its performance for uniform traffic by a numerical method and by computer simulations. The switch has N same input modules each of which is similar to the common shared buffer switch. N address buffers (ABs) in the input module are used for the N output, and the ABs for a certain output in different input modules are controlled by an external arbitrator. The MCTA arbitration is employed in order to reduce the required arbitration rate as well as to provide the guard time when the switch is operated at a very high-speed. In MCTA arbitration, the service order of two or more cells destined for the same output is determined by one arbitration, but the cells are transmitted one by one in each time slot.
Starting Page	536
Ending Page	540
File Size	474440
Page Count	5
File Format	PDF
ISBN	0780341988
DOI	10.1109/GLOCOM.1997.632602
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-11-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Asynchronous transfer mode Telecommunication switching Throughput Communication switching Telecommunication traffic Traffic control Queueing analysis
Content Type	Text
Resource Type	Article

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