NDLI: Implementing fair queueing in ATM switches. I. A practical methodology for the analysis of delay bounds

Content Provider	IEEE Xplore Digital Library
Author	Chiussi, F.M. Francini, A.
Copyright Year	1997
Description	Author affiliation: AT&T Bell Labs., Holmdel, NJ, USA (Chiussi, F.M.)
Abstract	The minimization of the implementation cost of cell schedulers which aim at approximating the generalized processor sharing (GPS) policy is a key practical issue in next-generation ATM switches. The total complexity of a GPS-related scheduler is a combination of the complexity of its system-potential function and the complexity involved in sorting the timestamps in order to select which cell should be transmitted. Several scheduling disciplines using a system-potential function of O(1) complexity have previously been introduced; still, the task of sorting the timestamps makes the cost of implementing a GPS-related scheduler quite significant. Thus, in practice, approximations are often introduced in the scheduler to reduce implementation complexity, typically at the cost of some degradation in the delay properties of the scheduler. In order to optimize the design so that such degradations are minimized, a tool is necessary, in the form of a general methodology to promptly and accurately analyze the delay properties. To truly aid in the design of the scheduler, such methodology should be simple to use in all practical situations. We present a methodology that fulfills this need. In the case of leaky-bucket constrained sources, we explicitly derive a general result for the delay bounds; our methodology, however, is applicable to other source models.
Starting Page	509
Ending Page	518
File Size	1413402
Page Count	10
File Format	PDF
ISBN	0780341988
DOI	10.1109/GLOCOM.1997.632598
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-11-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Queueing analysis Asynchronous transfer mode Switches Delay Processor scheduling Global Positioning System Degradation Bandwidth Scheduling algorithm Costs
Content Type	Text
Resource Type	Article

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