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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hung-Wei Chen Jiin-Chuan Wu Gwo-Sheng Huang Ji-Chien Lee Shin-Shi Chang |
| Copyright Year | 1995 |
| Description | Author affiliation: Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan (Hung-Wei Chen; Jiin-Chuan Wu) |
| Abstract | A new VLSI architecture of Reed Solomon decoder with erasure function and using a modified Euclid's algorithm to solve the key equation is presented. Its correction ability is 20 bytes/block. The block length is variable (from 96 bytes to 255 bytes). Hardware complexity is dependent only on 2t (number of parity check bytes). Due to the modified Euclid's algorithm, the hardware required for solving the RS code's key equation is reduced and the control circuitry simplified, thus this architecture is suitable for VLSI implementation. The decoder is reduced to a three stages pipelined structure. Its algorithms were simulated with C language, and over 6 million pattern were tested without mistake. The algorithm state machine (ASM) and architecture were verified with the Verilog description language, and over twelve thousand patterns were tested without mistake. |
| Starting Page | 1455 |
| Ending Page | 1459 |
| File Size | 405258 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780325095 |
| DOI | 10.1109/GLOCOM.1995.502643 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1995-11-14 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Very large scale integration Reed-Solomon codes Decoding Equations Computer architecture Hardware Parity check codes Error correction codes Polynomials Circuits |
| Content Type | Text |
| Resource Type | Article |
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