NDLI: Circuit Noise Effect on Sampling Clock in Software Radio IF Digitization

Content Provider	IEEE Xplore Digital Library
Author	Sun Lei An Jianping Wu Yanbo
Copyright Year	2007
Description	Author affiliation: Beijing Inst. of Technol., Beijing (Sun Lei; An Jianping; Wu Yanbo)
Abstract	IF digitization generally requires high resolution of analog-to-digital conversion. The timing jitter is a key concern and it's widely investigated in the published literatures. However, most of the issues mainly focused on the clock jitter with white Gaussian noise only. This paper present a more realistic analog-to-digital conversion analysis model based on the actual circuit noise conditions, particularly investigating on the clock jitter error with the combination of Gauss distribution noise and circuit noise (interference). An analytical expression for the A/D conversion with the combined clock jitter error is developed. The computer simulations are presented, which showed excellent agreement with the developed expression. Also, a real experiment brings forth a comprehensive evaluation in IF digitization.
Starting Page	1
Ending Page	5
File Size	2193287
Page Count	5
File Format	PDF
ISBN	1424410487
DOI	10.1109/ICMMT.2007.381413
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-04-18
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit noise Sampling methods Clocks Software radio Analog-digital conversion Gaussian noise Computer errors Timing jitter Gaussian distribution Interference software radio analog-to-digital converter clock jitter signal-to-noise ratio
Content Type	Text
Resource Type	Article

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