NDLI: Relaxation methods for analogue fault simulation

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Volume 2 - 1995

Routing in standard cells

Relaxation methods for analogue fault simulation

Symbolic function extraction and fault modelling of MOS circuits

Integrated circuit yield prediction

A proposal for the implementation of ternary digital circuits

A geometry independent CMOS transconductor: new method of linearization and AC analysis

CMOS VLSI realization of voltage-mode programmable analog cellular neural network

Modelling of ultrafast invertor logical circuit in BiMOS technology

Three-state BiCMOS buffers with positive feedback

Design of three-state logic for CMOS VLSI digital systems

Fault location in passive analog RC circuits by measuring impulse response

Topological level of symbolic approximation in analog circuit design

Hardware description languages for ALECSIS simulator

Sensor microsystems

Problem-oriented modeling of coupled physical effects in microtransducers and electronic devices

Production of sensors for different physical parameters on the base of all-purpose and unified technology

Production of Sensors for Different Physical Parameters on the Base of All-Pupose and Unified Techno

New generation of thermal infrared detectors

Sensors in diffusion plasma processing

Influence of impurity distribution on thermal coefficients of resistivity and piezoresistivity of diffused layers in silicon

Some aspects of design and fabrication of micromachined structures with high thermal resistivity

Resistance changes of SnO/sub 2/ thin films suitable for microelectronic gas sensors

Electronic model a thin film gas sensor (TFGS) based on SnO/sub 2/

Manufacturing peculiarities of the SnO/sub 2/ thin film gas sensors (TFGS)

Dynamic characteristics of silicon resistance temperature sensors

Glow-to-arc transition instability sensor in processing plasma

Capacitive pressure sensor for quasi-static conditions followed by A/D conversion

MOS device structure development for ULSI: low power/high speed operation

Low temperature characterization of silicon CMOS devices

Special mechanisms in thin film SOI MOSFETs

Microscopic theory of electronic noise in semiconductor materials and devices

A review of n-channel SOI transistor models

Avalanche phenomena in deeply depleted MOS capacitors

Relation between the leakage currents and defects in oxide and interface Si/SiO/sub 2/ in MOS devices

Effect of parasitic bipolar transistor in submicron MOSFETs

Modeling of high-injection effects in bipolar devices

A new approach to the modeling of minority-carrier transport in silicon p/sup +/nn/sup +/ diode

Problems in modelling multiterminal bipolar devices

Non-quasi-static bipolar transistor models for circuit simulators

Dependance of avalanche photodiode characteristics on active area geometry

Limit of D.C. performance of trench power MOSFETs

Simulation of transient turn-off characteristics of a trench emitter insulated gate bipolar transistor (IGBT)

Novel approximative analytical expressions for minority-carrier transit time including recombination

New investigation on silicon bipolar transistor at low temperature

A simple 2D analytical model of HEMT

Electronic transport properties of disordered quantum interference transistor

Numerical calculation of photodetector response time using Ramo's theorem

Analog universal active device: theory, design and applications

On the design of CFA-based sinusoidal oscillators

Filters and immittances using current-feedback amplifiers

OTA-based even-phase sinusoidal oscillators

High-frequency continuous-time filters design using a single operational transconductance amplifier

A new architecture of filter designed for testability

Computer-simulated design of an active microwave band-pass filter

Characterization of microwave planar transmission lines in multilayered medium

Design of a MMIC low noise amplifier at 10 GHz

Universal filter using both current and voltage followers

Design of digital allpass circuits for pulse compressing with Chebyshev phase

Modeling of coupled silicon beams

Symbolic approach in design of BaTiO/sub 3/-ceramics capacitive properties [bandpass filters]

High density multilayer interconnection concept of HDMI 3D descrambler

Design for analogue subscriber device with original subscriber line interface circuit design in multichip-module (MCM) technology

Design of ellipsoidal form permanent magnets

A research methodology in the field of computer engineering for VLSI

A new efficient design of the 2-to-1 multiplexer

Multilevel logic synthesis using algorithms based on natural processes

Speed-independent bit-serial multiplier

Testing of digital system in real-time applications

A VLSI implementation of multi-layer neural network with ternary activation functions and limited integer weights

A paradigm for massively parallel cellular architectures

A simulation analysis of hash-based algorithms for searching the ATM routing tables

Branch mechanisms in deep pipelines: reevaluating the existing solutions and proposing a new guideline

An approach to processor logic design using HDL for silicon compilation

An approach to real-time system design

Modeling and simulating real-time systems

Volume 1 - 1995

Relaxation methods for analogue fault simulation

Content Provider	IEEE Xplore Digital Library
Author	Zwolinski, M.
Copyright Year	1995
Description	Author affiliation: Dept. of Electron. & Comput. Sci., Southampton Univ., UK (Zwolinski, M.)
Abstract	The fault simulation of analogue circuits is an inherently difficult problem because of the lack of a simple fault model and because analogue simulation is itself slow. This paper describes a technique in which faulty and fault-free circuits are simulated together, such that if the terminal voltages of an active device are the same for the faulty and fault-free circuit, the model values calculated for the fault-free simulation are reused in the faulty simulation. A simple example is given in which it is shown that some savings in the CPU time are possible. Suggestions for further development of the algorithm to give substantial CPU savings are given.
Starting Page	467
Ending Page	471
File Size	479460
Page Count	5
File Format	PDF
ISBN	0780327861
DOI	10.1109/ICMEL.1995.500911
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-09-12
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Relaxation methods Circuit faults Circuit simulation Circuit testing Central Processing Unit Computational modeling Electronic equipment testing Digital circuits CMOS logic circuits Voltage
Content Type	Text
Resource Type	Article

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