NDLI: Test time reduction methods for yield test structures

Content Provider	IEEE Xplore Digital Library
Author	Hess, C. Read, H. Ren, J. Weiland, L.H. Jianjun Cheng Chock Gan Karbasi, H. Winters, S.
Copyright Year	2003
Description	Author affiliation: PDF Solutions Inc., San Jose, CA, USA (Hess, C.; Read, H.; Ren, J.; Weiland, L.H.)
Abstract	Complexity of integrated circuits has led to hundreds of millions of transistors, wiring lines, and layer to layer via connections on every chip. To allow accurate yield evaluation, it is required that process characterization test chips grow in complexity as well which has let to a significant bottleneck in testing them. Wafers that could be tested in less than two hours in a 0.35/spl mu/m technology now require 10 hours and more in a 0.13/spl mu/m technology. This paper will present methods how test structures can be redesigned to better support testing. Based on those we will present modified test algorithms that will significantly reduce the test time by 50% and more, which will accelerate data analysis and increases efficient use of parametric test systems.
Sponsorship	IEEE Electron Devices Soc
Starting Page	3
Ending Page	69
File Size	403061
Page Count	67
File Format	PDF
ISBN	0780376536
DOI	10.1109/ICMTS.2003.1197384
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-03-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System testing Circuit testing Electrical resistance measurement Semiconductor device measurement Integrated circuit testing Integrated circuit yield Wiring Data analysis Relays Failure analysis
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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