NDLI: MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines

Content Provider	IEEE Xplore Digital Library
Author	Drach, N. Seznec, A.
Copyright Year	1993
Description	Author affiliation: IRISA, Rennes, France (Drach, N.; Seznec, A.)
Abstract	Pipelining is a major technique used in high performance processors. But its effectiveness is reduced by the branch instructions. A new organization for implementing branch instructions is presented: the Multiple Instruction Decode Effective Execution (MIDEE) organization. All the pipeline depths may be addressed using this organization. MIDEE is based on the use of double fetch and decode, early computation of the target address for branch instructions and two instruction queues. The double fetch-decode concerns a pair of instructions stored at consecutive addresses. These instructions are then decoded simultaneously, but no execution hardware is duplicated; only useful instructions are effectively executed. A pair of instruction queues are used between the fetch-decode stages and execution stages; this allows to hide branch penalty and most of the instruction cache misses penalty. Trace driven simulations show that the performance of deep pipeline processor may dramatically be improved when the MIDEE organization is implemented: branch penalty is reduced and pipeline stall delay due to instruction cache misses is also decreased.
Starting Page	193
Ending Page	201
File Size	750350
Page Count	9
File Format	PDF
ISBN	0818652802
DOI	10.1109/MICRO.1993.282743
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-12-01
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Smoothing methods Pipeline processing Decoding Hardware Reduced instruction set computing Computer aided instruction Computer performance Degradation Delay effects Dynamic compiler
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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