NDLI: Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication

Content Provider	IEEE Xplore Digital Library
Author	Sassone, P.G. Wills, D.S.
Copyright Year	2004
Description	Author affiliation: Georgia Institute of Technology (Sassone, P.G.)
Abstract	In the modern era of wire-dominated architectures, specific effort must be made to reduce needless communication within out-of-order pipelines while still maintaining binary compatibility. To ease pressure on highly-connected elements such as the issue logic and bypass network, we propose the dynamic detection and speculative execution of instruction strands-linear chains of dependent instructions without intermediate fan-out. The hardware required for detecting these chains is simple and resides off the critical path of the pipeline, and the execution targets are the normal ALUs with a self-bypass mode. By collapsing these strings of dependencies into atomic macro-instructions, the efficiency of the issue queue and reorder buffer can be increased. Our results show that over 25% of all dynamic ALU instructions can be grouped, decreasing both the average reorder buffer occupancy and issue queue occupancy by over a third. Additionally, these strands have several properties which make them amenable to simple performance optimizations. Our experiments show average IPC increases of 17% on a four-wide machine and 20% on an eight-wide machine in Spec2000int and Mediabench applications. Finally, strands ease the IPC penalties of multicycle issue and bypass by reducing dependency pressures, providing opportunity for clock frequency gains as well.
Starting Page	7
Ending Page	17
File Size	350472
Page Count	11
File Format	PDF
ISBN	0769521266
ISSN	10724451
DOI	10.1109/MICRO.2004.16
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-12-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pipelines Computer architecture Hardware Logic Clocks Frequency Delay Computer aided instruction Reduced instruction set computing Instruction sets
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication

A pipelined architecture for logic programming with a complex but single-cycle instruction set

A Speculative Trace Reuse Architecture with Reduced Hardware Requirements

Pathlengths of SPEC benchmarks for PA-RISC, MIPS, and SPARC

Reduced instruction set computer architecture

Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication

Revolver: a high-performance MIMD architecture for collision free computing

Dynamic strands: collapsing speculative dependence chains for reducing pipeline communication.

MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines

Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication

Similar Documents

Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication

A pipelined architecture for logic programming with a complex but single-cycle instruction set

A Speculative Trace Reuse Architecture with Reduced Hardware Requirements

Pathlengths of SPEC benchmarks for PA-RISC, MIPS, and SPARC

Reduced instruction set computer architecture

Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication

Revolver: a high-performance MIMD architecture for collision free computing

Dynamic strands: collapsing speculative dependence chains for reducing pipeline communication.

MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines

Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication