NDLI: CoScale: Coordinating CPU and Memory System DVFS in Server Systems

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2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

2012 45th Annual IEEE/ACM International Symposium on Microarchitecture

Table of contents

Message from the General Chair

Message from the Program Chair

Program Committee

External Review Committee

FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory

Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access

Transactional Memory Architecture and Implementation for IBM System Z

Warped-DMR: Light-weight Error Detection for GPGPU

The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults

NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures

Cache-Conscious Wavefront Scheduling

Libra: Tailoring SIMD Execution Using Heterogeneous Hardware and Dynamic Configurability

Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor

Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation

KnightShift: Scaling the Energy Proportionality Wall through Server-Level Heterogeneity

Rethinking DRAM Power Modes for Energy Proportionality

CoScale: Coordinating CPU and Memory System DVFS in Server Systems

Predicting Performance Impact of DVFS for Realistic Memory Systems

Vector Extensions for Decision Support DBMS Acceleration

NOC-Out: Microarchitecting a Scale-Out Processor

SLICC: Self-Assembly of Instruction Cache Collectives for OLTP Workloads

Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks

AUDIT: Stress Testing the Automatic Way

Accurate Fine-Grained Processor Power Proxies

Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design

A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch

CoLT: Coalesced Large-Reach TLBs

NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers

Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance

Addressing End-to-End Memory Access Latency in NoC-Based Multicores

MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP

Composite Cores: Pushing Heterogeneity Into a Core

Control-Flow Decoupling

Spatiotemporal Coherence Tracking

Predicting Coherence Communication by Tracking Synchronization Points at Run Time

Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically

Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy

Improving Cache Management Policies Using Dynamic Reuse Distances

Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem

Inferred Models for Dynamic and Sparse Hardware-Software Spaces

SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations

Profiling Data-Dependence to Assist Parallelization: Framework, Scope, and Optimization

Neural Acceleration for General-Purpose Approximate Programs

Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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