NDLI: Thermal management of on-chip caches through power density minimization

Content Provider	IEEE Xplore Digital Library
Author	Ja Chun Ku Ozdemir, S. Memik, G. Ismail, Y.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA (Ja Chun Ku; Ozdemir, S.; Memik, G.; Ismail, Y.)
Abstract	Various architectural power reduction techniques have been proposed for on-chip caches in the last decade. However, these techniques mostly ignore the effects of temperature on the power consumption. In this paper, first we show that these power reduction techniques can be suboptimal when thermal effects are considered. Particularly, we propose a thermal-aware cache power-down technique that minimizes the power density of the active parts by turning off alternating rows of memory cells instead of entire banks. The decrease in the power density lowers the temperature, which in return, reduces the leakage of the active parts. Simulations based on SPEC2000 benchmarks in a 70nm technology show that the proposed thermal-aware architecture can reduce the total energy consumption by 53% compared to a conventional cache, and 14% compared to a cache architecture with thermal-unaware power reduction scheme. Second, we show a block permutation scheme that can be used during the design of caches to maximize the distance between blocks with consecutive addresses. By maximizing the distance between consecutively accessed blocks, we minimize the power density of the hot spots in the cache, and hence reduce the peak temperature. This, in return, results in an average leakage power reduction of 8.7% compared to a conventional cache without affecting the dynamic power and the latency. Overall, both of our architectures add no extra run-time penalty compared to the thermal-unaware power reduction schemes, yet they reduce the total energy consumption of a conventional cache by 53% and 5.6% on average, respectively.
Starting Page	11
Ending Page	293
File Size	371023
Page Count	283
File Format	PDF
ISBN	0769524400
DOI	10.1109/MICRO.2005.36
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-11-12
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Thermal management Energy management Energy consumption Threshold voltage Temperature Turning Delay Subthreshold current Switches Runtime
Content Type	Text
Resource Type	Article

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