NDLI: Near-optimal precharging in high-performance nanoscale CMOS caches

Content Provider	IEEE Xplore Digital Library
Author	Se-Hyun Yang Falsafi, B.
Copyright Year	2003
Description	Author affiliation: Comput. Archit. Lab., Carnegie Mellon Univ., Pittsburgh, PA, USA (Se-Hyun Yang; Falsafi, B.)
Abstract	High-performance caches statically pull up the bit-lines in all cache subarrays to optimize cache access latency. Unfortunately, such architecture results in a significant waste of energy in nanoscale CMOS implementations due to high leakage and bitline discharge in the unaccessed subarrays. Recent research advocates bitline isolation to control precharging of individual subarrays using bitline precharge devices. In this paper, we carefully evaluate the energy and performance trade-offs of bitline isolation, and propose a technique to exploit nearly its full potential to eliminate discharge and reduce overall energy in level-one caches. Cycle-accurate and circuit simulation results of a wide-issue superscalar processor indicate that: 1) in future CMOS technologies (e.g., 70 nm and beyond), cache architectures that exploit bitline isolation can eliminate up to 90% of the bitline discharge; 2) on-demand precharging (i.e., decoding the address and subsequently precharging the accessed subarrays) is not viable in level-one caches because precharging increases the cache access latency; and 3) our proposal for gated precharging to exploit subarray reference locality and precharging only the recently accessed subarrays eliminates nearly all of bitline discharge in nanoscale CMOS caches with only a 1% of performance degradation.
Sponsorship	IEEE TC-MARCH SIGMICRO
Starting Page	67
Ending Page	78
File Size	342167
Page Count	12
File Format	PDF
ISBN	076952043X
DOI	10.1109/MICRO.2003.1253184
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-12-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Isolation technology Delay Proposals Computer architecture Circuit simulation CMOS process Energy dissipation Out of order Random access memory
Content Type	Text
Resource Type	Article

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