NDLI: Increasing the size of atomic instruction blocks using control flow assertions

Content Provider	IEEE Xplore Digital Library
Author	Patel, S.J. Tung, T. Bose, S. Crum, M.M.
Copyright Year	2000
Description	Author affiliation: Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA (Patel, S.J.)
Abstract	For a variety of reasons, branch-less regions of instructions are desirable for high-performance execution. In this paper we propose a means for increasing the dynamic length of branch-less regions of instructions for the purposes of dynamic program optimization. We call these atomic regions frames and we construct them by replacing original branch instructions with assertions. Assertion instructions check if the original branching conditions still hold. If they hold, no action is taken. If they do not, then the entire region is undone. In this manner an assertion has no explicit control flow. We demonstrate that using branch correlation to decide when a branch should be converted into an assertion results in atomic regions that average over 100 instructions in length, with a probability of completion of 97%, and that constitute over 80% of the dynamic instruction stream. We demonstrate both static and dynamic means for constructing frames. When frames are built dynamically using finite sized hardware, they average 80 instructions in length and have good caching properties.
Starting Page	303
Ending Page	313
File Size	1010152
Page Count	11
File Format	PDF
ISBN	076950924X
ISSN	10724451
DOI	10.1109/MICRO.2000.898080
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-12-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Size control Hardware Computer aided instruction Optimizing compilers Proposals
Content Type	Text
Resource Type	Article

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