NDLI: Efficient checker processor design

Content Provider	IEEE Xplore Digital Library
Author	Chatterjee, S. Weaver, C. Austin, T.
Copyright Year	2000
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., MI, USA (Chatterjee, S.)
Abstract	The design and implementation of a modern microprocessor creates many reliability challenges. Designers must verify the correctness of large complex systems and construct implementations that work reliably in varied (and occasionally adverse) operating conditions. In our previous work, we proposed a solution to these problems by adding a simple, easily verifiable checker processor at pipeline retirement. Performance analyses of our initial design were promising, overall slowdowns due to checker processor hazards were less than 3%. However slowdowns for some outlier programs were larger. The authors closely examine the operation of the checker processor. We identify the specific reasons why the initial design works well for some programs, but slows others. Our analyses suggest a variety of improvements to the checker processor storage system. Through the addition of a 4 k checker cache and eight entry store queue, our optimized design eliminates virtually all core processor slowdowns. Moreover, we develop insights into why the optimized checker processor performs well, insights that suggest it should perform well for any program.
Starting Page	87
Ending Page	97
File Size	1196518
Page Count	11
File Format	PDF
ISBN	076950924X
ISSN	10724451
DOI	10.1109/MICRO.2000.898061
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-12-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Process design Testing Formal verification Pipelines Microprocessors Space technology Retirement Performance analysis Hazards Design optimization
Content Type	Text
Resource Type	Article

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