NDLI: The filter cache: an energy efficient memory structure

Content Provider	IEEE Xplore Digital Library
Author	Kin, J. Munish Gupta Mangione-Smith, W.H.
Copyright Year	1997
Description	Author affiliation: Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA (Kin, J.)
Abstract	Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occupy a large portion of the chip area. Not surprisingly, these caches often consume a significant amount of power. In many applications, such as portable devices, low power is more important than performance. We propose to trade performance for power consumption by filtering cache references through an unusually small L1 cache. An L2 cache, which is similar in size and structure to a typical L1 cache, is positioned behind the filter cache and serves to reduce the performance loss. Experimental results across a wide range of embedded applications show that the filter cache results in improved memory system energy efficiency. For example, a direct mapped 256-byte filter cache achieves a 58% power reduction while reducing performance by 21%, corresponding to a 51% reduction in the energy-delay product over conventional design.
Starting Page	184
Ending Page	193
File Size	1220600
Page Count	10
File Format	PDF
ISBN	0818679778
ISSN	10724451
DOI	10.1109/MICRO.1997.645809
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-12-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy efficiency Clocks Microprocessors Energy consumption Read-write memory Power filters Filtering Performance loss Delay MOSFETs
Content Type	Text
Resource Type	Article

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