NDLI: Voltage-Driven Multilevel Programming in Phase Change Memories

Content Provider	IEEE Xplore Digital Library
Author	Cabrini, A. Braga, S. Manetto, A. Torelli, G.
Copyright Year	2009
Abstract	In the multilevel (ML) storage approach, any single cell in a memory array is programmed to one among n≫2 predetermined different states. To exploit the ML approach in the case of phase change memories (PCMs), it is necessary to accurately program the active chalcogenide layer to a number of different partially crystallized states so as to precisely allocate the electrical resistance of the cell in the range from the maximum to the minimum available value. In this paper, we experimentally investigate the characteristics of two voltage-driven programming algorithms, namely, the single-pulse and the (multi-pulse) staircase-up (SCU) programming algorithm, from a ML storage point of view. To this end, we analyze the impact of the amplitude and the time length of applied voltage pulses on the programmed resistance, showingthat the SCU algorithm appears to be a promising candidate for PCM ML storage.
Starting Page	3
Ending Page	6
File Size	172119
Page Count	4
File Format	PDF
ISBN	9780769537979
DOI	10.1109/MTDT.2009.11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-31
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage Phase change memory Phase change materials Electric resistance Crystallization Amorphous materials Temperature MOSFETs Electronic equipment testing Phased arrays voltage-driven programming phase change memories multilevel programming
Content Type	Text
Resource Type	Article

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