NDLI: A Wide-VDD Embedded SRAM for Dynamic Voltage Asynchronous Systems

Content Provider	IEEE Xplore Digital Library
Author	Shu-Meng Yang Meng-Fan Chang Kung-Ting Chen Wen-Chin Wu Yuan-Hua Chu Ting-Sheng Chao Ming-Bin Chen Ping-Cheng Chen
Copyright Year	2009
Abstract	Voltage-dependent timing skews in precharge and sensing activities cause functional failure and reduce the speed of asynchronous SRAM. Data-dependent bitline leakage current further increases the timing skews and reduces the yield of asynchronous SRAM. A dual-mode self-timed (DMST) technique is developed for asynchronous SRAM to eliminate the timing-skew-induced failures and speed overhead across various process, voltage and temperature (PVT) conditions. Measurements demonstrated that the DMST technique can be operated continuously over a wide range of supply voltages, from 39.4% to 151.5% (or 212.1%, given device durability) of the nominal supply voltage (3.3V). The fabricated macros also confirmed that the DMST technique is scalable for various bitline lengths, and offers the same area overhead as conventional sense-tracking-only replica-column schemes.
Starting Page	20
Ending Page	24
File Size	279368
Page Count	5
File Format	PDF
ISBN	9780769537979
DOI	10.1109/MTDT.2009.14
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-31
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Timing System-on-a-chip Voltage control Degradation Decoding Circuits Conferences System testing Chaotic communication destructive read Timing skew asynchronous SRAM bitline leakage
Content Type	Text
Resource Type	Article

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