NDLI: Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology

Content Provider	IEEE Xplore Digital Library
Author	Wenfeng Zhao Yajun Ha Chin Hau Hoo Alvarez, A.B.
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore, Singapore (Wenfeng Zhao; Yajun Ha; Chin Hau Hoo; Alvarez, A.B.)
Abstract	High functional yield is one of the key challenges for subthreshold standard cell designs. Device upsizing is a commonly used but suboptimal method due to its overheads in energy and area. In this paper, we propose a robustness-driven intra-cell $mixed-V_{t}$ design methodology (MVT-ULV) for the robust ultra-low voltage operation. It uses low threshold voltage transistors in the weak pulling network of logic gates to enhance the robustness. It guarantees the high functional yield with the minimum energy/area overheads. We demonstrate on a commercial 65nm CMOS process that, our proposed design methodology shows up to 60mV and 110mV robustness improvement at 300mV power supply voltage over the commercial library cells and the cells built with previous Leakage-Minimization $mixed-V_{t}$ methods (MVT-LM) under the same cell area constraints, respectively. In addition, the proposed MVT-ULV library enables ITC'99 benchmark circuits to show on average 30.1% and 78.1% energy-efficiency improvement when compared to the libraries built with the device-upsizing methods and the previous MVT-LM methods under the same yield constraints, respectively.
Starting Page	323
Ending Page	328
File Size	1994169
Page Count	6
File Format	PDF
e-ISBN	9781479912353
DOI	10.1109/ISLPED.2013.6629317
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-04
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Robustness Libraries Logic gates Flip-flops Transistors Logic design Standards multi-Vt design Intra-cell mixed-Vt subthreshold circuits standard cell library yield enhancement
Content Type	Text
Resource Type	Article

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