NDLI: Low-voltage low-overhead asynchronous logic

Content Provider	IEEE Xplore Digital Library
Author	Sridharan, A. Sechen, C. Jafari, R.
Copyright Year	2013
Description	Author affiliation: Dept. of Electr. Eng., Univ. of Texas at Dallas, Richardson, TX, USA (Sridharan, A.; Sechen, C.; Jafari, R.)
Abstract	A new delay-bounded asynchronous logic technique aimed at maximizing reliability at very low voltages is proposed. Compared to previous asynchronous logic approaches, the area and nominal delay overheads are small. Conventional standard cell libraries and conventional logic synthesis tools are used. The bounding delay elements used by the asynchronous controller feature programmable delays that are initially set based on static timing analysis. However, the delay elements are updated on-the-fly during actual operation of the circuit, resulting in strong resiliency even at low voltages and with extreme variations. Several benchmark circuits were implemented with the new asynchronous design flow using the 45nm TI process. Monte Carlo analysis demonstrates the expected resiliency. Compared to the equivalent synchronous circuits, the asynchronous versions have area overheads averaging 40%, although much smaller for large circuits. Nominal delay overheads average about 10%.
Starting Page	261
Ending Page	266
File Size	990218
Page Count	6
File Format	PDF
e-ISBN	9781479912353
DOI	10.1109/ISLPED.2013.6629306
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-04
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delays Flip-flops Throughput Logic gates Radiation detectors Benchmark testing Libraries low voltage Asynchronous logic de-synchronization
Content Type	Text
Resource Type	Article

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