NDLI: Theory and practical implementation of harmonic resonant rail driver

Content Provider	IEEE Xplore Digital Library
Author	Joong-Seok Moon Athas, W.C. Beerel, P.A.
Copyright Year	2001
Description	Author affiliation: Univ. of Southern California, Los Angeles, CA, USA (Joong-Seok Moon)
Abstract	This paper presents a new algorithm for designing efficient harmonic resonant rail drivers. The circuit solution is coupled to a standard pulse source and uses only discrete passive components. It can thus be externally tuned to minimize the consumed power in the target IC. A new efficient algorithm based on current-fed pulse-forming network theory is proposed to find the value of each discrete component for a target frequency and a given load capacitance. The proposed driver topology can be used to generate any desired periodic 50% duty-cycle waveform by superimposing multiple harmonies of the desired waveform, however, this paper focuses on the generation of square-wave clock signals. We have tested the driver with a capacitive load between 38.3 pF and 97.8 pF. The overall dissipation for our second-order harmonic rail driver is 19% of fCV/sup 2/ at 15 MHz and 97.8 pF load.
Sponsorship	ACM SIGDA
Starting Page	153
Ending Page	158
File Size	558815
Page Count	6
File Format	PDF
ISBN	1581133715
DOI	10.1109/LPE.2001.945392
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-08-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Resonance Rails Signal generators Algorithm design and analysis Driver circuits Coupling circuits Pulse circuits Frequency Capacitance Network topology
Content Type	Text
Resource Type	Article

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