NDLI: Low-power technology mapping for mixed-swing logic

Content Provider	IEEE Xplore Digital Library
Author	Dragone, N. Rutenbar, R.A. Carley, L.R. Zafalon, R.
Copyright Year	2001
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA (Dragone, N.)
Abstract	Mixed-swing logic employs multiple power supply rails and device threshold voltages and allows us to create richer cell libraries with a wider range of power/speed tradeoffs. However, mapping onto such a library with a conventional technology mapper will not exploit the full potential of a mixed-swing methodology. To remedy this, we have developed a new technology mapping tool that specifically targets mixed-swing logic. Our approach combines (1) efficient clustering and cluster-level delay budgeting for the uncommitted logic, with (2) an exhaustive search for the optimal cover that is rendered practical by the clustering process. Power savings up to 3X have been demonstrated with our mixed-swing solutions versus single power supply implementations.
Sponsorship	ACM SIGDA
Starting Page	291
Ending Page	294
File Size	519744
Page Count	4
File Format	PDF
ISBN	1581133715
DOI	10.1109/LPE.2001.945420
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-08-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	CMOS logic circuits Timing Power supplies Threshold voltage Dynamic voltage scaling Rails Delay Logic devices Libraries Energy consumption
Content Type	Text
Resource Type	Article

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