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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Poate, J.M. Agarwal, A. Rubin, L.M. Natsuaki, N. Sugitani, M. |
| Copyright Year | 2001 |
| Description | Author affiliation: Axcelis Technol. Inc., Beverly, MA, USA (Poate, J.M.) |
| Abstract | We review the many challenges that lie ahead for ion implantation. Continued device scaling requires the formation of ever-shallower, low-resistivity junctions. Recent trends in conventional implant and RTA processing, such as the use of ultra-low energy implants and spike anneals, allow these technologies to continue to be used for the formation of ultra-shallow junctions that meet the ITRS requirements for at least the 70 nm node. Successful fabrication of sub-100 nm devices will also require an understanding of the use of species such as indium and antimony for ultra-precise dopant placement. There will be an expanded use of high energy implantation. Applications here include triple well isolation for memory structures, and buried layer implants for W gettering. We discuss non-traditional applications of ion implantation. These include implants for the fabrication of SOI materials and implants into vertical device structures. We conclude with a discussion of the implications of these technologies on the future of the ion implantation business. |
| Sponsorship | Japan Soc. Appl. Phys.-Silicon Technol. Div. |
| Starting Page | 1 |
| Ending Page | 5 |
| File Size | 549144 |
| Page Count | 5 |
| File Format | |
| ISBN | 4891140194 |
| DOI | 10.1109/IWJT.2001.993813 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2001-11-29 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Japan Soc. Of Applied Physics |
| Subject Keyword | Ion implantation Implants Annealing MOSFETs Boron Fabrication Silicon on insulator technology Manufacturing Degradation Indium |
| Content Type | Text |
| Resource Type | Article |
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