NDLI: Performance Evaluation of AES Algorithm on Various Development Platforms

Content Provider	IEEE Xplore Digital Library
Author	Parikh, C. Patel, P.
Copyright Year	2007
Description	Author affiliation: Univ. of Texas at San Antonio, San Antonio (Parikh, C.; Patel, P.)
Abstract	With the rapid growth of low-cost, low-power handheld devices with wireless capability, more and more devices connect to wireless networks. This warrants secured data exchange and authentication to take place during the connection. 802.11i security scheme is becoming a de- facto standard of future WLAN, which uses AES algorithm in both encryption and authenticity of payload data. Cryptographic transformations of AES are computationally intensive, consuming significant power. Most of the published AES implementations target high- end products with multi-gigabit throughputs and have no regards for power consumption. Low-end products, including handheld devices like PDA rarely need more than 200 Mbps data transfer rate which necessitates alternative implementation of AES algorithm, with the aim of reducing power consumption and increasing the handsets' battery life. In this paper we study and compare the outcome obtained from implementing AES algorithm on various platforms. We present results obtained through profiling the implemented algorithm on platforms like FPGA, Desktop PC (Microsoft Visual Studio) and handheld device (UIQ SDK for Symbian OS along with Metrowerks CodeWarrior). Our comparison shows that the 32-bit hardware implementation of AES on FPGA supports the required throughput and consumes less power allowing fully charged PDA to remain connected to WLAN for a longer duration.
Starting Page	1
Ending Page	6
File Size	671337
Page Count	6
File Format	PDF
ISBN	9781424411092
DOI	10.1109/ISCE.2007.4382134
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-20
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Handheld computers Wireless LAN Cryptography Throughput Energy consumption Personal digital assistants Field programmable gate arrays Communication system security Wireless networks Authentication Decryption FPGA AES WLAN SDK Symbian Encryption
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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