NDLI: Integrated electro-chemical mechanical planarization (Ecmp) for future generation device technology

Content Provider	IEEE Xplore Digital Library
Author	Economikos, L. Wang, X. Sakamoto, X. Ong, P. Naujok, M. Knarr, R. Chen, L. Moon, Y. Neo, S. Salfelder, J. Duboust, A. Manens, A. Lu, W. Shrauti, S. Liu, F. Tsai, S. Swart, W.
Copyright Year	2004
Description	Author affiliation: IBM Microelectron., White Plains, NY, USA (Economikos, L.)
Abstract	A novel copper (Cu) planarization process, Ecmp, integrating electro-chemical mechanical polishing capability on a 300mm CMP platform with low down force conventional polishing processes is being developed and evaluated on low-k CVD devices. In the integrated Ecmp process, the bulk Cu is removed by electro-chemical mechanical polishing at a high rate which is controlled by applied charge and is independent of down force (0.3psi bulk Cu removal step). The Ecmp process removes topography efficiently and produces a thin planarized Cu film across the wafer to match that of the conventional Cu planarization step. The Cu thickness profile produced by electro-chemical planarization allows the conventional planarization process to clear remaining Cu with low dishing across the wafer. Therefore, an excessive dielectric removal for dishing correction is not required, making the process extendible to ultra-low k dielectrics that require a protective capping layer to be retained after polishing. Experiments are conducted to evaluate the planarization efficiency, film profile, and endpoint control, cost of consumables, pattern density sensitivity and defect density. The mechanical and electrical results indicate that Ecmp enables the planarization of dual damascene structures with minimal dielectric erosion and defect density.
Sponsorship	IEEE Electron Devices Soc
Starting Page	233
Ending Page	235
File Size	244988
Page Count	3
File Format	PDF
ISBN	0780383087
DOI	10.1109/IITC.2004.1345759
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-06-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Planarization Copper Dielectrics Fabrication Semiconductor device modeling Cleaning Protection Process control Costs Manufacturing processes
Content Type	Text
Resource Type	Article

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